1. Technical Field
The present invention generally relates to the manufacturing of integrated circuits. More specifically, the present invention relates to a method for oxidizing three-dimensional silicon patterns of very small dimensions.
2. Discussion of the Related Art
“Patterns of very small dimensions” is here used to designate elements in relief having at least one dimension—their width or their length—smaller than 100 nm. Insulated gates of MOS type transistors are considered hereafter as a non-limiting example of such three-dimensional patterns, the gate length being smaller than 100 nm.
FIGS. 1A to 1D illustrate, in simplified partial cross-section view, different steps of a known method for forming a MOS transistor in a P-type doped single-crystal silicon substrate 1.
As illustrated in FIG. 1A, a thin insulating layer 2 is first formed, after which a polysilicon layer 3 is deposited. Layers 3 and 2 are then successively etched according to a same pattern, to define the insulated gate of the transistor. Gate 2-3 is defined to have a length GL of at most 100 nm.
At the next steps, illustrated in FIG. 1B, an insulating layer, generally a multilayer 4 comprising a silicon oxide (SiO2) internal portion 5 and a silicon nitride (Si3N4) external portion 6, is formed. Internal portion 5 generally results from a thermal oxidation of the silicon forming gate electrode 3, followed by the deposition of a silicon oxide layer. External portion 6 results from the deposition of a silicon nitride layer.
Then, as illustrated in FIG. 1C, multilayer 4 is anisotropically etched to only be left in place on the sides of gate 2–3. First so-called offset spacers 7 are thus formed, which extend gate length GL by a value w. Spacers 7 are then used as a mask upon forming, in substrate 1, of lightly-doped source/drain regions (LDD) 8 by implantation of N-type dopants. The constraints resulting from the forming of first spacers 7 and their function will be discussed hereafter.
At the next steps, illustrated in FIG. 1D, at least one insulating layer is deposited and anisotropically etched, so that second spacers 10 are formed on either side of gate 2-3. Then, heavily-doped N-type source drain regions 13 (HDD) are formed in LDD regions 8. In this implantation, spacers 10 are used as masks.
Such a method and the resulting structures have disadvantages linked to offset spacers 7.
In technologies with a short gate length (GL<100 nm), the first spacers avoid for LDD regions 8 to join in the portion of substrate 1 underlying insulated gate 2-3. This risk is significant due to the fact that the forming of LDD regions 8 of a junction depth of at most 20 nm is delicate.
The forming of first spacers 7 results from a compromise between various constraints. In particular, spacers 7 must have an accurately determined length w/2, smaller than 20 nm, preferably on the order of from 5 to 10 nm. If length w/2 is too short, there is an overlapping between the two LDD regions 8 and the transistor source and drain are short-circuited. Conversely, if length w/2 is too long, length CL of the channel is too long and the transistor exhibits inferior electric performance, especially with a high on-state resistance.
The desired accuracy cannot be obtained with the method of FIGS. 1A to 1C, especially since length w/2 depends on the anisotropic etch methods used (FIGS. 1B–1C) to define spacers 7. These methods are poorly controlled and result in the forming of inhomogeneous spacers. Indeed, on the one hand, it is not known to remove the planar portions of multilayer 4 without etching or overetching its vertical portions intended to form spacers 7. Such an overetching reduces length w/2 of spacers 7 with respect to the initial thickness of multilayer 4. Such an overetching is not necessarily symmetrical for a given transistor and, further, when the density of formed transistors is significant, it is inhomogeneous for the different transistors.
The problem described hereabove for transistor gates is more generally encountered as soon as a thin oxide layer is desired to be formed on silicon patterns while the pattern density is very high.